A hardware accelerator for IEEE 802.15.4 Time-Slotted Channel Hopping transceiver

Time-Slotted Channel Hopping (TSCH), an operational mode of the IEEE 802.15.4e standard, imposes a high workload on embedded processor, mainly due to its precise timing. The limited processor edge device cannot satisfy considerable memory footprint and computational complexity caused by functions that need timing in protocol stack. Moving such duties hardware seems be viable path towards offloading releasing resource used for running firmware related implementation upper layers stack as well application. In this work, TSCH accelerator is designed integrated within digital baseband 802.15.4 transceiver. whole system implemented targeting TSMC 65 nm technology. has efficient interface totally configurable software. It efficiently controls transceiver, frees up cycles, reduces interrupt callback processor. Therefore, makes it possible use cheaper or operate lower clock speed which results power consumption. analysis shows that, minimal setting accelerator, only 0.1% added consumption overhead increases 5.6% supporting three parallel slotframes widely multi-hop networks. return, relaxed processing interrupts are required software-based implementation.